IEEE 1014-1987 (R2008) pdf free.IEEE Standard for A Versatile Backplane.
IEEE 1014 A data transfer bus (DTB) cycle that is used to transfer 1,2,3, or 4 bytes from a slave to a master. The cyclebegins when the master broadcasts an address and an address modifier. Each slave captures the address and the addressmodifier, and verifies if it will respond to the cycle. lf it is intended to respond, it retrieves the data from its internalstorage, places it on the data bus and acknowledges the transfer. The master then terminates the cycle.
write cycle: A data transfer bus(DTB) cycle that is used to transfer 1,2, 3, or 4 bytes from a master to a slave.Thecycle begins when the master broadcasts an address and an address modifier and places data on the data transfer bus(DTB). Each slave captures the address and the address modifier and verifies if it will respond to the cycle. If it isintended to respond, it stores the data and then acknowledges the transfer. The master then terminates the cycle.
block read cycle: A data transfer bus (DTB) cycle that is used to transfer a block of bytes ranging in number from 1to 256 bytes from a to a master. This transfer is executed by using a string of 1-,2-, or 4-byte data transfers. Once theblock transfer is initiated,the master does not release the DTB until all of the bytes have been transferred. Thisoperation differs from a string of read cycles insofar as the master broadcasts only one address and one addressmodifier (at the beginning of the cycle).The slave then increments this address on each transfer so that the data for thenext transfer is retrieved from the next higher location.
block write cycle: A data transfer bus (DTB) cycle used to transfer a block of bytes ranging in number from 1 to 256bytes from a master to a slave. It uses a string of 1-,2-, or 4-byte data transfers. Once the block transfer is initiated, themaster does not release the DTB until all of the bytes have been transferred. It differs from a string of write cyclesinsofar as the master broadcasts only one address and one address modifier (at the beginning of the cycle).The slavethen increments this address on each transfer so that the data from the next transfer is stored in the next higher location.read-modify-write cycle: A data transfer bus (DTB)cycle that is used to both read from, and write to, a slave locationwithout permitting any other master to access that location.This cycle is most useful in multiprocessing systems wherecertain memory locations are used to provide semaphore functions.
address-only cycle: A data transfer bus (DTB) cycle that consists of an address broadcast, but does not have a datatransfer. Slaves do not acknowledge address-only cycles and masters terminate the cycle without waiting for anacknowledgment.
interrupt acknowledge cycle: A data transfer bus (DTB) cycle, initiated by an interrupt handler,that reads a status/IDfrom an interrupter.An interrupt handler generates this cycle whenever it detects an interrupt request from aninterrupter and it has control of the DTB.IEEE 1014 pdf download.