IEEE P802.3CT/D3.0-2020 pdf free.Draft Standard for Ethernet Amendment: Physical Layers and Management Parameters for 100 Gb/s Operation over DWDM systems.
When read as a one, biL 1.2201.10 indicates that the Inverse RS-FEC described in Clause 152 has locked and aligned lane 2 of the IFEC service interface. When read as a zero. bit 1.2201.10 indicates that the Inverse RS-FEC has not locked and aligned lane 2 of the IFEC sen ice interface. This bit reflects the state of amps_lockI2] (see 152.5.2.1).
45.2.1.186ab.5 FEC AM lock 1(1.2201.9)
When read as a one, bit I .2201.9 indicates that the Inverse RS-FEC dcscribcd in Clause 152 has locked and aligned lane I of the IFEC service interface, When read as a zero, bit 1.2201.9 indicates that the Inverse RS-FEC has not locked and aligned lane I of the IFEC service interface. This bit reflects the state of amps_locki I] (see 152.5.2.1).
45.2.1.186ab.6 FEC AM lock 0 (1 .2201.8)
When read as a one, bit 1.2201.8 indicates that the Inverse RS-FEC described in Clause 152 has locked and aligned lane 0 of the IFEC service intcrficc, When read as a zero, bit 1,2201,8 indicates that the Inverse RS-FEC has not locked and aligned lane 0 of the IFEC sen ice interface. This bit reflects the state of amps lock(0] (see 152.5.2.1).
45.2.1.186ab.7 Inverse RS-FEC high SER (1.2201.2)
When bit 1.2200.1 (IFEC_bypass_indication_cnablc) is set to one, bit 1.2201.2 is set to one lithe number of RS-FEC symbol errors in a window of 8192 codewords exceeds the threshold (sec 152.5.2.3) and is set to zero otherwise. The bit is set to zero if bit 1.2200.1 (IFEC_bypass_indication_enablc) is set to zero. This bit shall be implemented with latching high behavior.
45.2.1.186ab.8 IFEC bypass indication ability (1 .2201 .1)
The Reed-Solomon decoder may have the option to perform error detection without error indication (see 152.5.2.3) to reduce the delay contributed by the Inverse RS-FEC sublaycr. This bit is set to one to indicate that the decoder has this ability to bypass the error indication function. The bit is set to zero ii this ability is not supported.
45.2.1.186ab.9 IFEC bypass correction ability (1 .2201.0)
The Reed-Solomon decoder may have the option to perform error detection without error correction (see 152.5.2.3) to reduce the delay contributed by the Inverse RS.FEC sublayer. This bit is set to one to indicate that the decoder has this ability to bypass error correction. The bit is set to zero if this ability is not supported.IEEE P802.3CT/D3.0 pdf download.