IEEE 1596-1992 pdf free.IEEE Standard for Scalable Coherent Interface (SCI).
IEEE 1596 Purpose: To define an interface standard for very high performance multiprocessor systems that supports a coherentshared-memory model scalable to systems with up to 64K nodes.This standard is to facilitate assembly of processor,memory, l/O, and bus adaptor cards from multiple vendors into massively parallel systems with throughputs rangingup to more than 1o12 operations per second.
Scope: This standard will encompass two levels of interface, defining operation over distances less than 10 m.Thephysical layer will specify electrical, mechanical, and thermal characteristics of connectors and cards. The logicallevel will describe the address space,data transfer protocols，cache coherence mechanisms，synchronizationprimitives, control and status registers,and initialization and error recovery facilities.
The preceding statements were those submitted to and approved by the IEEE Standards Board as the definition of thesCI project. These goals have been met and exceeded: support for message-passing was added, and the operatingdistance is not limited to 10 m.(The intent of that limitation was to make clear that this is not yet-another Local AreaNetwork.)The real distinction between SCI and a network has more to do with the memory-acces-based model SCl uses and thedistributed cache-coherence model.The practical operating distance depends more on the throughput and performanceneeded than on any absolute limit built into the specification—very long links would yield unacceptable performancefor many users (but perhaps not all).
In particular, the fiber-optic physical layer can extend the SCI paradigm over distances long enough to link a computerto its I/0 devices, or to link several nearby processors. No arbitrary length limit would be appropriate, but practicalconsiderations including the throughput requirements and the cost of transmitters and receivers will set the lengths thatpeople consider useful.
A very-high-priority goal was that SCl be cost-effective for small systems as well as for the massively parallel onesmentioned in the purpose statement above. SCY’s low pin count and simple ring implementation make medium-performance,few-processor systems easier to build with SCl than with bused backplane systems; a two-layerbackplane should be sufficient, and three layers should be enough to support the optional geographical addressingmechanism.The SClinterface,complete with transceivers,fits into a single ICpackage that includes much of the logicneeded to support the cache-coherence protocols.This economy for small systems leads to the expectation that SCIprocessor boards will be built in high volume, making them inexpensive enough to be assembled in large numbers forbuilding supercomputers at low cost.IEEE 1596 pdf download.